1. Field of Invention
This invention relates to non-volatile memory, and more particularly relates to a new structure of NAND flash memory unit or 3D-array capable of reducing Vt-shift of the select transistor of NAND flash memory subjected to erasing.
2. Description of Related Art
The NAND structure is widely used in the design of non-volatile memory (NVM) apparatus to increase the storage density. A NAND flash memory unit usually includes a string of memory cells connected in series, and a select transistor couple between a terminal of the string of memory cells and an S/D region. When the cells are trapping-type cells, i.e., each cell has a charge-trapping layer, the select transistor also has a charge-trapping layer.
The NAND flash memory can be erased by applying 0V to the cell gates and the gate of the select transistor, and a high positive voltage to the S/D regions. For a high voltage difference is established between the gate of the select transistor and the channel region in the erasing, holes are injected in or electrons drawn out of the trapping layer under the gate of the select transistor, so the threshold voltage (Vt) of the select transistor is shifted adversely affecting later operations of the NAND flash memory.
Nothing, however, herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.